1. Field of the Invention
The embodiments of the present invention relate to a technical field of display, more particularly, relate to an array substrate, a method for manufacturing the same, and a display device.
2. Description of the Related Art
In Advanced-Super Dimensional Switching (ADS) technology, a multi-dimensional electric field is formed by a parallel electric field and a longitudinal electric field, the parallel electric field is produced by coplanar edges of pixel electrodes or coplanar edges of a common electrode, and the longitudinal electric field is produced between the pixel electrodes and the common electrode. With the multi-dimensional electric field, all alignment liquid crystal molecules within the liquid crystal cell between the pixel electrodes and the common electrode, as well as above the pixel electrodes or the common electrode, are rotated and switched, and therefore, working efficiency of plane-orientation liquid crystals is improved, and the light transmittance is increased.
The ADS technology may improve image quality of TFT-LCD, and has the advantages of high transmission rate, wide view angle, high aperture rate, low aberration, faster response time, no push Mura and the like.
An ADS display device is formed by ceiling a color filter substrate and an ADS array substrate. As shown in FIG. 1, the ADS array substrate comprises a substrate; and a thin film transistor, a pixel electrode 11 and a common electrode 12 which are provided on the substrate. The pixel electrode 11 is an upper strip electrode, and the common electrode 12 is a lower plate electrode. During manufacturing, a source-drain metal layer forms source/drain electrodes 172 of the thin film transistor, and a data line 171; a gate metal layer forms a gate line 13 (a portion of the gate line 13 is used as a gate electrode of the thin film transistor), a common electrode line 14, and gate pads 141; and then a connection line 15 is formed in a second transparent conductive layer (for example, 2nd ITO layer, for forming the pixel electrodes 11). The connection line 15 connects the common electrode line 14 with the common electrode 12 through via holes 16 in the gate pads 141.
If the common electrode line 14 and the gate line 13 are not provided in the same layer, manufacturing processes increases; however, if they are provided in the same layer, the aperture rate is reduced by the common electrode line 14 and the gate pads 141, and connection resistance of the gate line is increased by the via holes for connecting the common electrode line 14 with the common electrode 12.